Throw away your clock!

UPC/DAC VLSI Systems Design

E-mail: cad-vlsi@ac.upc.es
Departament d'Arquitectura de Computadors
Universitat Politècnica de Catalunya
Campus Nord, Mòdul D6
Jordi Girona 1-3
08034 BARCELONA, Spain
Telephone: +34 3 4017001
Fax: +34 3 4017055

Number of visitors to this page since Nov 96: n+1

The VLSI Systems Design Team

Jordi Cortadella
(E-mail jordic@lsi.upc.es)
Rosa Badia
(E-mail rosab@ac.upc.es)
Fermín Sánchez
(E-mail fermin@ac.upc.es)
Enric Pastor
(E-mail enric@ac.upc.es)
Oriol Roig
(E-mail oriol@ac.upc.es)
Marco A. Peña
(E-mail marcoa@ac.upc.es)

Former Members

Enric Musoll
(E-mail enric@arador.nsc.com)

Publications

CAD Tools

petrify - synthesize a Petri net.
versify - VERiFY a Speed-Independent circuit, a Signal Transition Graph or a Petri net.

Related links

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Last modified: March 1998, by oriol@ac.upc.es